The presentation consists of 3 parts. First, we discuss the purpose of Design Verification and verification methods in general. We follow with an overview of SystemVerilog Assertions (SVA), followed by a description of the structured way of implementing simulation /emulation test benches based on the SystemVerilog Unified Verification Methodology (UVM).
Ed Cerny earned his Ph.D. in EE from McGill University in Montreal in 1975. He was a Professor in the EE Department of Concordia University until 1978 and then in the Computer Science Department of Universite de Montreal until 2000. He worked at Nortel Networks from 2000 to 2001 and then joined Synopsys, Inc., in Marlborough, MA. His primary responsibility is in assertion implementation and deployment, both in simulation and property checking. He is a Member of the IEEE P1800 (SystemVerilog) SV-AC standardization committee. He retired as Synopsys Scientist in 2017, after 16 years in the Verification Group.
Chris Spear is an instructor with Mentor Graphics, teaching engineers how to verify designs using SystemVerilog and UVM. He is the author of the best-selling book, SystemVerilog for Verification. Previously he has been a verification engineer for Intel and an Application Consultant for Synopsys and Cadence. In his spare time he volunteers with the Rotary Club of Nashoba Valley and the Boy Scouts, and bikes over mountains.