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Seminar: Ting-wei Tang

“Simulation of Junctionless Gate-All-Around Nanowire Transistors using Wigner Transport Equation: Results and Numerical Issues”

Date/Time: 

Thursday, November 30, 2017 - 11:30am to 12:30pm

Presenter: 

Ting-wei Tang, Emeritus Professor, University of Massachusetts, Amherst

Location: 

Marcus 201 Conference Room

Details: 

Junctionless nanowire transistors (JLNWTs) have attracted significant attention of researchers because they are easy to fabricate and show superior performance over the conventional junction transistors. However, as their size shrinks, it becomes more and more difficult to achieve a satisfactory OFF-state characteristic. It can be easily seen that there would be a limit on how short the gate length can be. A shorter gate results in a shorter potential barrier between the source (S) and drain (D): when the barrier becomes too short, the tunneling current through it can deteriorate the OFF-state characteristic in an obvious way.

In this presentation, we investigate the effect of this S-D tunneling current on the device performance of JLNWTs using the Wigner transport equation (WTE), a quantum-mechanical analogy of the classical Boltzmann transport equation (BTE). Especially, we focus on their subthreshold characteristics such as subthreshold slope (SS). Not only numerical issues but also associated limitations of WTE that are critical in the analysis are to be presented and discussed.