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Seminar: Wilson Snyder

“Speedy Reference Models, Direct from RTL”

Date/Time: 

Monday, October 23, 2017 - 4:00pm to 5:15pm

Presenter: 

Wilson Snyder, Cavium, Inc.

Location: 

ELab II Auditorium

Details: 

Hardware/software co-design requires an accurate model of the hardware.  Verilator, an open source simulator, allows teams to convert the Verilog HDL used to build their silicon directly into C++ classes for simulation and co-design.  The primary author of Verilator discusses how the tool has evolved, it's usage by many of the leading processor vendors, its internal workings, and how it may evolve in the future to include high-speed multi-threaded execution.

Wilson Snyder is a Distinguished Engineer and lead chip architect with Cavium, Inc. in Marlboro, Massachusetts, USA.  A graduate of Rensselaer, he has held ASIC design and microprocessor architecture positions at Digital Semiconductor, Maker Communications, Sun Microsystems, and SiCortex.  He makes numerous contributions to public domain engineering tools, such as Verilog-Mode for Emacs, and Verilator, available off his Veripool.com web site.