309E Knowles Engineering Bldg
University of Massachusetts
151 Holdsworth Way
Amherst MA 01003-9284
B.Sc., Technion - Israel Institute of Technology, 1967; M.Sc., 1970; D.Sc., 1975
Fault-tolerant systems, Power-aware Multi-core architectures, Secure Cryptographic systems and Digital computer arithmetic.
· A. Barenghi, C. Hocquet, D. Bol, F-X. Standaert, F. Regazzoni and I. Koren, "A Combined Design-Time/Test-Time Study of the Vulnerability of Sub-Threshold Devices to Low Voltage Fault Attacks," to appear, IEEE Transactions on Emerging Topics in Computing, 2014.
· S. Wimer and I. Koren, "Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating," IEEE Trans. on VLSI Systems, pp. 771-778, April 2014.
· I. Koren and C. M. Krishna, "Temperature-Aware Computing," (Invited Paper), Sustainable Computing: Informatics and Systems, Vol. 1, No. 1, pp. 46-46, March 2011.
· F. Regazzoni, L. Breveglieri, P. Ienne and I. Koren, "Interaction between Fault Attack Countermeasures and the Resistance against Power Analysis Attacks," in Fault Analysis in Cryptography, M. Joye and M. Tunstall (Eds.), Chapter 15, pp. 257-273, Information Security and Cryptography Series, Springer Lecture Notes in Computer Science, Vol. XVI, Springer-Verlag, 2012.
· R. Rodrigues, A. Annamalai, I. Koren and S. Kundu, "Improving Performance per Watt of Asymmetric Multicore Processors via Online Program Phase Classification and Adaptive Core Morphing," ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 18, pp. 1-23, Jan. 2013.
· Textbook: I. Koren and C. M. Krishna, Fault-Tolerant Systems, Morgan-Kaufman, San Francisco, CA, 2007.
· Textbook: I. Koren, Computer Arithmetic Algorithms, 2nd Edition, A. K. Peters, Natick, MA, 2002.
· Active pixel with built in self-repair and redundancy. US Patent No. 7,408,578
· Reducing processor energy consumption using compile-time information. US Patent No. 7,278,136.
Fellow of IEEE and the Computer Society, Member of ACM.
IEEE Fellow, Fellow of Japan Society for the Promotion of Science.
Associate editor of VLSI Design Journal, Sustainable Computing: Informatics and Systems. Past Associate editor of IEEE Computer Architecture Letters, IEEE Transactions on VLSI and IEEE Transactions on Computers. Co-Guest Editor of Special Issues of the IEEE Trans. on Computers on Computer Arithmetic, July 2000, and on Fault Diagnosis and Tolerance in Cryptography, June 2006; and of a Special Issue of the Sustainable Computing: Informatics and Systems Journal. Keynote address at the 25th IEEE Symp. on Defect and Fault Tolerance in VLSI & Nanotechnology Systems, Oct. 2012. Steering Committee member - IEEE Symposium on Computer Arithmetic, IEEE Symposium on Defect and Fault Tolerance in VLSI & Nanotechnology Systems, and IEEE Green Computing Conference. General Chair - The 17th IEEE Symposium on Computer Arithmetic, June 2005. Co-general chair - FDTC 2005-2013, Fault Diagnosis and Tolerance in Cryptography. Program Committee co-chair - IGCC 2011 - International Green Computing Conference. Program Committee member - The 43rd IEEE/IFIP Conference on Dependable Systems and Networks (DSN),} June 2013; The 2003-2013, 16th-21th IEEE Symposiums on Computer Arithmetic; The 2013 ACM Reliable and Convergent Systems Conference; The 2012 ACM Research in Applied Computation Symposium, October 2012; 9th ACS/IEEE Conference on Computer Systems and Applications, 2011, 12th IEEE Conference on High Performance Computing and Communications, 2010, 11 - 16 Euromicro Conference on Digital System Design, 2008-2013. Member of NSF Computer Engineering Research Proposal Review Panels, 2002, 2003, 2004 and 2009. Program Committee member - The 2004-2013 IEEE Symposium on Defect and Fault Tolerance in VLSI Systems. Program Committee member - The 2004-2010 IEEE Symposium on Application-specific Systems.