Maciej J. Ciesielski
307 Knowles Engineering Bldg
University of Massachusetts
151 Holdsworth Way
Amherst MA 01003-9284
M.S., Warsaw Technical University, 1974;
Ph.D., University of Rochester, 1984
Electronic Design Automation for digital systems. Formal methods in Computer-Aided Design. Behavioral and RTL synthesis. Formal verification and design validation
M. Ciesielski, W. Brown, D. Liu, A. Rossi, ``Function Extraction fromArithmetic Bit-level Circuits'', IEEE Computer Society AnnualSymposium on VLSI (ISVLSI), pp. 356-361, July 2014.
T. Ahmad, M. Ciesielski, ``Fast STA Prediction-based Gate-Level TimingSimulation'', DATE-2014, pp. 248.1-248.6, March 2014.
M. Ciesielski, W. Brown, A. Rossi,``Arithmetic Bit-level Verification using Network Flow Model'',Haifa Verification Conference, HVC-2013, LNCS 8244, pp. 327-343, Nov. 2013.D. Kim, M. Ciesielski, S. Yang, "MULTES: Multi-Level Temporal-parallelEvent-driven Simulation", IEEE Trans. on CAD of Integrated Circuits andSystems 32(6): pp. 845-857 (2013).
M. Ciesielski, D. Gomez-Prado, Q.Ren, J. Guillot, E. Boutillon,``Optimization of Data Flow Computations using Canonical TEDRepresentation'', IEEE Trans. on Computer-Aided Design, Vol. 28,No. 9, pp. 1321 - 1333, Sept. 2009.
IEEE, senior member
Doctorat Honoris Causa, Université de Bretagne Sud, Lorient, France, May 2008
Associate Department Head (since Sept. 2006), ECE Graduate Seminar Committee, ECE Personnel Committee, ECE Department Accreditation ABET Task Force, Member of Technical Program Committees at several international conferences and workshops (VLSI, ICCAD, IWLS, ECECS, CFV), Session and Topic Chair at DAC 2006, CFV 2008.