Maciej J. Ciesielski
307 Knowles Engineering Bldg
University of Massachusetts
151 Holdsworth Way
Amherst MA 01003-9284
M.S., Warsaw Technical University, 1974;
Ph.D., University of Rochester, 1984
Electronic Design Automation for digital systems. Formal methods in Computer-Aided Design. Behavioral and RTL synthesis. Formal verification and design validation
- D. Kim, M. Ciesielski, K. Shim, S.Yang, ``Temporal Parallel Simulation: A Fast Gate-Level HDL Simulation using Higher Level Models'', IEEE Design, Automation and Test in Europe (DATE'11), March 2011.
- M. Ciesielski, D. Gomez-Prado, Q.Ren, J. Guillot, E. Boutillon, ``Optimization of Data Flow Computations using Canonical TED Representation'', IEEE Trans. on Computer-Aided Design, Vol. 28, No. 9, Sept. 2009, pp. 1321 - 1333.
- M. Ciesielski, A.M. Jabir, D. Pradhan, ``Canonical Graph-based Representations for Verification of Arithmetic and Data Flow Designs'', in Practical Design Verification, ed. D.K. Pradhan, I.G. Harris, Cambridge University Press, 2009, pp. 173-245.
- M. Ciesielski, P. Kalla, and S. Askar, ``Taylor Expansion Diagrams: A Canonical Representation for Verification of Dataflow Designs'', IEEE Transactions on Computers, Vol. 55, No. 9, Sept. 2006, pp. 1188-1201.
- Z. Zeng, K.R. Talupuru, and M. Ciesielski, ``Functional Test Generation based on Word-level SAT'', in Journal of Systems Architecture, Elsevier Publishers, Vol. 51, Issue 8, August 2005, pp. 488-511.
IEEE, senior member
Doctorat Honoris Causa, Université de Bretagne Sud, Lorient, France, May 2008
Associate Department Head (since Sept. 2006), ECE Graduate Seminar Committee, ECE Personnel Committee, ECE Department Accreditation ABET Task Force, Member of Technical Program Committees at several international conferences and workshops (VLSI, ICCAD, IWLS, ECECS, CFV), Session and Topic Chair at DAC 2006, CFV 2008.