Sandip Kundu

Professor

Knowles 309J

309J Knowles Engineering Bldg
University of Massachusetts
151 Holdsworth Way
Amherst MA 01003-9284

kundu@ecs.umass.edu

(413) 577-3309

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Education

B. Tech. Electronics & Elec. Comm. Eng., Indian Institute of Technology, 1984;
Ph.D., University of Iowa, 1988

Research

VLSI Circuit Design & Test, CAD for VLSI circuit Design & Test, Design & Testing of highly scaled circuits, Design of Resilient Computing Systems

Research Area:

Computer & Embedded Systems

Publications

Sandip Kundu and Aswin Sreedhar, "Nanoscale CMOS VLSI Circuits: Design for Manufacturability," ISBN: 978-0071635196, McGraw-Hill Professional, 2010
Omer Khan, Sandip Kundu, "Thread Relocation: A Runtime Architecture for Tolerating Hard Errors in Chip Multiprocessors," IEEE Transactions on Computers, pp. 651-665, May, 2010.
Kunal P. Ganeshpure and Sandip Kundu, "On ATPG for Multiple Aggressor Crosstalk Faults,", IEEE Transactions on CAD, vol. 29, pp. 774-787, May 2010
Alodeep Sanyal, Ashesh Rastogi, Wei Chen, Sandip Kundu, "An Efficient Technique for Leakage Current Estimation in Nanoscaled CMOS Circuits Incorporating Self-Loading Effects," IEEE Transactions on Computers, pp. 922-932, July, 2010

On Weighted Random Pattern Self-Test Hardware. US Patent No: 5,297,151
A CMOS transistor network to gate level model extractor for simulation, verification and test generation, US Patent No: 5,629,858
System and method for testing internal nodes of an integrated circuit at any predetermined machine cycle, US Patent No: 5,793,777
Technique for sorting high frequency integrated circuits, US Patent No: 5,796,751
Constrained Signature-Based Test, US Patent No: 6,510,398
System for rearranging plurality of memory storage elements in a computer process to different configuration upon entry into a low power mode of operation, US Patent No: 6,715,091

Honors

Fellow of the IEEE, IEEE Computer Society Distinguished Visitor, Fellow of Japan Society for the Promotion of Science

Best Paper Awards:

Aswin Sreedhar, Sandip Kundu, "On Linewidth-based Yield Analysis for Nanometer Lithography," Design Automation and Test in Europe, 2009
The Best of ICCAD – 20 Years of Excellence in Computer Aided Design
S. Kundu, S. M. Reddy and N. Jha, “On The Design of Robust Multiple Fault Testable CMOS Combinational Logic Circuits” IEEE International Conference on Computer Aided Design, Santa Clara, November 1988)
S. Kundu and S. M. Reddy, “Design of TSC checkers for implementation in CMOS technology,” Int. Conference on Computer Design, Boston, October 2-4, 1989

Experience

Institutional & Professional Service:

Technical Program Chair: Asian Test Symposium (2010), ICCD (2000) General Chair: ICCD (2001), VLSI (2005), Technical Program Committee Member of several IEEE sponsored conferences, Keynote speaker at DCIS (2000), GMM Workshop (2000, 2005)

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VLSI CAD Lab

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