Professor Maciej Ciesielski of our Electrical and Computer Engineering Department and his former graduate student Dr. Cunxi Yu – currently a post-doctoral researcher at the École Polytechnique Fédérale de Lausanne in Switzerland – won the 2017 Hardware Security Contest (HACK@DAC) at the Design Automation Conference, the world’s number one conference in the area of electronic design automation (EDA). The Design Automation Conference was held from June 18 to 22 at the Austin Convention Center in Texas. See conference website
Ciesielski and Yu’s winning paper introduces “Countermeasures Against Timing Side-Channel Attack of Integrated Circuits,” using EDA techniques.
According to the website of the Design Automation Conference, the background of the HACK@DAC contest is that the globalization of integrated circuit (IC) design is making designers and users of IC and intellectual property (IP) re-assess their trust in hardware. As the IC design flow spans the globe — driven by cost-conscious consumer electronics — hardware is increasingly prone to side channel analysis, reverse engineering, IP piracy, IC counterfeiting, and malicious modifications (i.e. hardware Trojans). The semiconductor industry routinely loses over $4 billion annually due to one or more of these attacks.
Participating teams in the HACK@DAC contest try to mimic the behavior of a malicious or secure-unaware CAD engineer. Their objective is to show that reasonable modifications to CAD algorithms can have unintended security consequences.
As Ciesielski and Yu explain, “This paper proposes to evaluate re-synthesis and statistical timing analysis (STA) techniques and their impact on timing side-channel attacks. We introduce a metric to evaluate whether the design is threatened by timing attack using the timing slack distribution generated by STA tool. With this metric, we explore whether it is possible to incrementally optimize the design against timing attack using logic synthesis techniques, such as retiming and technology mapping.”
Ciesielski and Yu write in their paper that side-channel attacks are known threats to cryptography devices, such as smart cards and mobile phones. Those techniques can retrieve the secret information from side-channel leakages by analyzing the characters of the hardware. For example, differential power analysis is a side-channel attack which involves statistically analyzing power-consumption measurements from a crypto-system. Differential fault analysis can obtain the key with a significantly reduced number of experiments by observing erroneous outputs by injecting fault. Such information also can be retrieved by timing side-channel attack, i.e. by measuring variations in the execution time. A timing attack is an example of an attack that exploits the data-dependent behaviors of the actual implementation, instead of its specification.
Professor Ciesielski received his M.S. in Electrical Engineering from Warsaw Technical University, Poland, in 1974, and his Ph.D. in Electrical Engineering from the University of Rochester in 1983. From 1983 to 1986 he worked at GTE Laboratories on the SILC silicon compiler project. He joined the University of Massachusetts Amherst in 1987. He teaches and conducts research in the area of electronic design automation, and specifically in synthesis, simulation, and formal verification of VLSI circuits and systems. In 2008, he received a Doctorate Honoris Causa from the Université de Bretagne Sud in Lorient, France, for contributions to the development of EDA tools for high-level synthesis.
Yu, before doing his current post doc in Switzerland, received his Ph.D. in Computer System Engineering from UMass Amherst in 2017 under the supervision of Professor Ciesielski. During the period of his graduate studies, 2013-2017, he published 12 peer-reviewed papers in international conferences, two IEEE journal articles, and has two more journal publications in review. He was a research intern with the IBM Thomas J. Watson Research Center in 2015 and 2016. (July 2017)