The University of Massachusetts Amherst
University of Massachusetts Amherst

Search Google Appliance

Links

ECE Grad Student Wins Best Paper Award

Prasad Shabadi, a graduate student in the Electrical and Computer Engineering Department, won the Best Student Paper Award at the IEEE/ACM International Symposium on Nanoscale Architectures 2011 in San Diego, California, with a paper entitled “Spin Wave Functions Nanofabric Update.” The article describes research on “a better, game-changing way to improve system-level performance” of computer devices “based on non-equilibrium physical phenomena and wave interactions, e.g., spin waves.” The authors were Shabadi, Alexander Khitun, Kin Wong, P. Khalili Amiri, Kang L. Wang, and ECE Professor C. Andras Moritz.

As the summary of the paper explains, “Over the past few decades, the growth in IC industry is primarily driven by CMOS technology scaling. Technology scaling has enabled an exponential increase in on-chip transistor density with improved performance and reduced power dissipation. However, as CMOS technology scaling is reaching its fundamental limits, researchers around the globe are forced to look beyond CMOS for new ideas. New devices based on spin-FETs, molecular-level physical phenomena, and FET devices based on emerging nanoscale materials, e.g., built with nanowires, graphene ribbons, and carbon nanotubes are being actively investigated.

“The main focus in the device community, however, has been on improving the intrinsic delay, minimizing switching power and leakage in a single device, often assuming that the rest of the paradigm to design chips could remain almost unchanged from CMOS. For example, even with computation paradigms based on new types of physical phenomena (i.e. alternate state variables), what forms the basic device is often envisioned as a simple controlled/gated switch. The computational paradigm relies then on fairly conventional mindset: building a first gate out of these switches with relatively low fan-in and fan-out, cascading these into multiple levels with larger fan-in and more complex logic functions and then forming blocks of conceptually interesting components like an ALU, etc. What is notable is that by the time these blocks are composed, due to the many levels of logic and wiring requirements, the original goal of having a small switching delay, while still important, has a considerably reduced impact on overall performance. Clearly, system-level performance does not always scale in proportion to the individual device performance.

“Can there be then a better, game-changing way to improve system-level performance? While there are many possible pathways to attack the nanoscale fabric problem, we propose to shift the focus towards new types of devices that can be made more functional than simple switches. For example, imagine if it would be possible to devise devices that are able to implement arbitrary logic operations or even logic functions with high fan-in and fan-out without proportionally increasing delay, power and area.

“One physical fabric approach that has this potential is based on non-equilibrium physical phenomena and wave interactions, e.g., spin waves. With no physical movement of charge particles for computation, the spin wave technology is expected to be extremely energy efficient. Information is encoded in the phase of the wave and computation is based on the principle of superposition. In 2010, we first introduced the fabric concept of SPWFs (Spin Wave Functions) wherein logic functions are implemented in a single step. Our initial evaluations have shown that the SPWF-based designs are expected to have orders of magnitude area and power benefits vs. corresponding state-of-art CMOS-based designs. In our current work presented at NANOARCH 2011, we have provided a comprehensive progress update (both experimental and design) on the Spin Wave Functions nanofabric. Voltage based control and generation of spin waves has been experimentally demonstrated at room temperature with only 60aJ of energy per operation. Several SPWF topologies and circuit styles are explored with an integrated fabric-circuit development mindset. Our efforts towards developing new architectures using spin wave logic places strong emphasis on cross-cutting issues and integrated exploration across multiple design levels aimed at solving problems from a particular fabric perspective. This work is a collaborative effort with Professor Kang’s group at UCLA and Professor Khitun at UCR.”

The IEEE/ACM international symposium on nanoscale architectures (NANOARCH) is the annual cross-disciplinary forum for the discussion of novel post-CMOS nanocomputing directions. The symposium seeks papers on innovative ideas for solutions to the principal challenge facing integrated electronics in the 21st century - how to design, fabricate, and integrate nanosystems to overcome the fundamental limitations of CMOS. (July 2011)