C. Andras Moritz | Electrical and Computer Engineering

Professor

Office: Knowles 207

Mailing Address:
207 Knowles Engineering Bldg
University of Massachusetts
151 Holdsworth Way
Amherst, MA 01003-9284

andras@ecs.umass.edu

(413) 545-2442

Personal Academic Website

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Education

Research Scientist at MIT, 1997-2000
Ph.D., Royal Institute for Technology, Stockholm, Sweden, 1998
M.S., Technical University, Cluj-Napoca, Ro., 1985

Research

Exploring of nanoscale fabrics for beyond-CMOS ICs and associated unconventional models of computation. Current projects are based on 3D nanowire, neuromorphic, and spintronics-based Bayesian architectures and have an integrated device-circuit-architecture focus.

Research Area:

Computer and Embedded Systems

Publications

[1] M. Rahman, P. Narayanan, S. Khasanvis, J. Nicholson, and C. A. Moritz, “Experimental Prototyping of Beyond-CMOS Nanowire Computing Fabrics”, in Proceedings of IEEE/ACM International Symposium on Nanoscale Architectures, NYC, 2013

[2] S. Khasanvis, M. Rahman, and C. A. Moritz, "Heterogeneous Graphene-CMOS Ternary Content Addressable Memory", Special Issue Computing with Nanotechnology, Journal of Parallel and Distributed Computing, in press, 2013

[3] P. Shabadi, S. Rajapandian , S. Khasanvis, and C. A. Moritz, "Design of Spinwave Functions Based Logic Circuits", in SPIN, eds. Stuart Parkin, vol. 2, no. 3, World Scientific Publishing Company, 2012

[4]P. Narayanan, J. Kina, P. Panchapakeshan, C. O. Chui and C. A. Moritz, Integrated Device-Fabric Explorations and Noise Mitigation in Nanoscale Fabrics, IEEE Transactions on Nanotechnology, vol. 11, no. 4, pp. 687 -700, Jul. 2012

[5] Csaba Andras Moritz, et al, “Fault-tolerant Nanoscale Processors on Semiconductor Nanowire Grids”, in IEEE Transactions on Circuits and Systems I, Special Issue on Nanoscale Circuits and Architectures, Volume: 54, Issue: 11, pp 2422-2434, November 2007.

[6] Csaba Andras Moritz, Donald Yeung, and Anant Agarwal, “SimpleFit: A Framework for Analyzing Design Tradeoffs in Raw Architectures”, in IEEE Transactions on Parallel and Distributed Systems, May, 2001.

Honors

8 patents issued.

Best Paper Awards:

IEEE/ACM International Symposium on Nanoscale Architectures Best Paper Award 2013. Best 20 Last 25 Years Paper Award at IEEE Symposium on Custom Computing Machines 2013. IEEE Computer Society Symposium on VLSI 2008 Best Paper Award. Best Student Paper Award at IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems 2011. Best Student Paper Award at IEEE/ACM International Symposium on Nanoscale Architectures 2011. Best Student Paper IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems 2010.

Society Memberships:

IEEE

Experience

Institutional & Professional Service:

External: Director of the Nanoscale Computing Fabrics Laboratory; Co-leader of the Nanoelectronics Technical Research Group at the CHM/NSEC NSF-sponsored nanoscience center, General Chair of Nanoarch IEEE/ACM International Symposium in 2011, 2012, 2013 and 2014; Associate Editor (AE) for IEEE Transactions on Nanotechnology; Guest Editor of the Elsevier JPDC Special Issue: Computing with Future Nanotechnology in 2014; Guest Editor of a Special Issue/Section on Neuromorphic/brain-like Computing with Nanotechnology in IEEE Transactions on Nanotechnology in 2014; member of the ACM/SIGDA technical committee on emerging technologies; Chair of the Steering Committee for IEEE Transactions on Multi-Scale Computing Systems; AE of IEEE Transactions on Computers between 2001-2006; Theme Lead for Nanofabrics at the FENA/FCRP-DARPA nanoarchitectonics research center 2009-2012.

Internal: Chair ECE Department Strategic Planning, Chair ECE Faculty Search, Member of Executive Committee UMass CHM Center.

Links

Homepage:

http://www.ecs.umass.edu/ece/andras

Lab Affiliation:

Nanoscale Computing Fabrics Lab

Center for Hierarchical Manufacturing

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