Maciej J. Ciesielski

Professor

Associate Dept. Head

Knowles 307

307 Knowles Engineering Bldg
University of Massachusetts
151 Holdsworth Way
Amherst MA 01003-9284

ciesiel@ecs.umass.edu

(413) 545-0401

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Education

M.S., Warsaw Technical University, 1974;
Ph.D., University of Rochester, 1984

Research

Electronic Design Automation for digital systems. Formal methods in Computer-Aided Design. Behavioral and RTL synthesis. Formal verification and design validation

Research Area:

Computer & Embedded Systems

Publications

M. Ciesielski, W. Brown, D. Liu, A. Rossi, "Function Extraction from Arithmetic Bit-level Circuits," IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 356-361, July 2014.
T. Ahmad, M. Ciesielski, "Fast STA Prediction-based Gate-level Timing Simulation," pp. 248.1-248.6, March 2014.
M. Ciesielski, W. Brown, A. Rossi, "Arithmetic Bit-level Verification Using Network Flow Model," Haifa Verification Conference, HVC-2013, LNCS 8224, pp. 327-343, Nov. 2013.
D. Kim, M. Ciesielski, S. Yang, "MULTES: Multi-Level Temporal-Parallal Event-Driven Simulation," IEEE Trans. on CAD Integrated Circuits and Systems 32(6): pp. 845-857 (2013).
M. Ciesielski, D. Gomez-Prado, Q. Ren, J. Guillot, E. Boutillon, "Optimization of Data Flow Computations Using Canonical TEDRepresentation," IEEE Trans. on Computer-Aided Design, Vol. 28, No. 9, pp. 1321-1333, Spet. 2009

Honors

Doctorat Honoris Causa, Université de Bretagne Sud, Lorient, France, May 2008

Society Memberships:

IEEE, senior member

Experience

Institutional & Professional Service:

Associate Department Head (since Sept. 2006), ECE Graduate Seminar Committee, ECE Personnel Committee, ECE Department Accreditation ABET Task Force, Member of Technical Program Committees at several international conferences and workshops (VLSI, ICCAD, IWLS, ECECS, CFV), Session and Topic Chair at DAC 2006, CFV 2008.

Links

Homepage:

http://www.ecs.umass.edu/ece/labs/vlsicad/ciesielski.html

Lab Affiliation:

VLSI CAD Lab

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