The University of Massachusetts Amherst
University of Massachusetts Amherst

Search Google Appliance

Links

Sachin Bhat Wins Best Paper Award at IEEE Symposium

Sachin Bhat

Sachin Bhat

Doctoral Student Sachin Bhat of the Electrical and Computer Engineering (ECE) Department won the Best Paper Award at the 2021 Institute of Electrical and Electronics Engineers Computer Society Annual Symposium on Very-large-scale Integration (VLSI), a premier VLSI conference. Bhat, whose faculty advisor is ECE Professor Csaba Andras Moritz, was the primary author of the winning paper.

The research in the winning paper is geared to develop the next generation of technology based on the standard complementary metal–oxide semiconductor (CMOS), which is currently reaching its physical limits in terms of miniaturization and performance.

As Bhat explains the research described in the winning paper, “Digital integrated circuits based on CMOS are the cornerstone pieces of electronic devices fueling a wide range of human endeavors. Nevertheless, the current two-dimensional, CMOS-based designs are not only facing challenges due to miniaturization limitations, but also new applications such as artificial intelligence (AI) require much higher density interconnects and performance.”

According to Bhat, in response to these challenges, most three-dimensional integration tactics would try to sandwich these two-dimensional approaches into stacks, a solution that brings only an incremental benefit.

“In contrast,” says Bhat, “our SkyBridge 2.0 work aims at developing the next generation of CMOS technology based on a fine-grained, vertically integrated, three-dimensional CMOS. Our paper shows the proposed three-dimensional integration technology, vertical CMOS circuit design and validation, and demonstrates its scalable manufacturing pathway through industry standard process emulation.”

The winning paper, titled “SkyBridge-3D-CMOS 2.0: IC Technology for Stacked-Transistor 3D ICs Beyond FinFETs,” addresses several key challenges when scaling to sub-5 nanometer node and beyond. The research is envisioned to provide an integrated solution to critical technology aspects such as characterization of three-dimensional fabric components, scalable CAD tool flow, a compact model for the surrounding-gate transistor, and a scalable manufacturing process.

Other authors of the paper in addition to Bhat and Moritz include ECE graduate students Mingyu Li and Sourabh Kulkarni, along with undergraduate Sounak 'Shaun' Ghosh.

All the authors of the winning paper belong to the Nanoscale Computing Fabrics Lab, headed by Moritz. As Moritz describes his lab’s work, “Our research addresses the fundamental problem of how to realize new kinds of computation with emerging technology. Our focus is on co-development of technology and models of computation post-CMOS, targeting digital and AI frameworks.” (August 2021)